Wide Band Universal PLL/Clock Source Model UPL-240
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DST - RF, Microwave and Hi-speed Logic Engineering House RF amd Microwave custom engineering
DST - RF, Microwave and Hi-speed Logic Engineering House RF amd Microwave custom engineering
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Wide Band Universal PLL/Clock Source
Model UPL-240
UPL-240 is wideband oscillator utilizing high performance PLL(Phase Locked Loop).
It can generate signal from 4.5MHz -240MHz frequency phase locked with external
or internal clock.Output frequencycan be calcurated : Fout=Fin*N/R ,simply setting
R and N value.

The frequency can be controlled by parallel data such as BCD SW or serial data
which can be connected to PC communication port and can be stored into the
EEPROM and in case of setting the power off, and on again, the stored frequency
can be output.

Output phase adjustment capability enables to make desired phase delay to the
external reference clock. Clock signal which is video line(H-sync) locked can be


FEATURES
  • The phase locked output frequency can be determined by Main divider(N) and
    Reference divider(R) as follows; Fout=Fin*N/R
  • Wide range of external clock generation capability ; 10KHz -25MHz
  • Phase comparator edge (fall or rise) can be selected.
  • Output phase adjustment capability
  • Setting can be stored into EEPROM to eleminate data load when power on.
  • Phase comparator disable funtion enables to free-run vco.
  • Compact module

APPLICATION
  • Various clock source
  • Phase shifter of clock signal
  • Signal generator
  • Regeneration of pixel clock


  SPECIFICATION
Power Supply +5V ±5%, 50mA
Output Level OUT1 : more than 1.5Vp-p (50ohm termination : more than 0.75Vp-p )
OUT2 : TTL/CMOS
Output frequency range OUT1 : 18MHz - 240MHz
OUT2 : 4.5MHz - 60MHz (1/4 of OUT1 frequency)
Phase comparator frequency range 10KHz - 200KHz
Output wave duty OUT1 : 50% ±20%
OUT2 : 50% ± 5%
Jitter Phase comparator frequency 10KHz :less than ±10n (OUT2)
Phase comparator frequency 100KHz less than ±2nS (OUT2)
External clock frequency range 10KHz - 25MHz
Frequency Accuracy Internal clock : ±50ppm, 0-50 degrees C
External clock : depends on external clock accuracy
Spurious less than -40dB (except harmonics)
Reference divider range 1 - 1023
Output main divider range 65-2047
Output phase 0/90/180/270 degrees(OUT2)
Fine phase control max.10-15nS min. resolution :1/14
Non-Voltile memory save times more than 10,000
Frequency Control Parallel input nine(9) control pins BCD input
Serial input two(2) data pins signal level TTL
9600BPS, 8 bit, w/o parity
1 stop bit
ASCII 7 digit numeric data and delimitter.
Frequency switching time 300mS (untill locked and stable condition from end of setting )
Dimensions 50x35x12mm

Refer to the User's Manual

  UPL-240_u.pdf

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